Engineering Journal Publications

2005-2009

D. Lee, H, Kim, M. Rahimi, D. Estrin and J.D. Villasenor, ” Energy-Efficient Image Compression for Resource-Constrained Platforms,” IEEE Transactions on Image Processing, vol. 18. no. 9, pp. 2100-2113, September 2009.

D. Lee, R.C.C. Cheung, W. Luk, and J. D. Villasenor, ” Hierarchical Segmentation for Hardware Function Evaluation ,” IEEE Transactions on VLSI Systems, vol. 17, no. 1, pp. 103-116, January 2009.

D. Lee and J. D. Villasenor, ” Optimized Custom Precision Function Evaluation for Embedded Processors ,” IEEE Transactions on Computers, vol. 58, no. 1, pp. 46-59, January 2009.

K. Soroushian, S. Priyadarshi, and J. Villasenor, “H.264 Parameter Optimizations for Internet Based Distribution of High Quality Video,” Proceedings of the SMPTE 2008 Annual Technical Converence, Oct. 28-30, 2008.

S. Priyadarshi, K. Soroushian and J. Villasenor, “Rich Metadata Description for Interactivity and Dynamic User-Generated Information,” Proceedings of the SMPTE 2008 Annual Technical Converence, Oct. 28-30, 2008.

H. Kim, M. Rahimi, D. Lee, D. Estrin, and J. D. Villasenor, “Energy-aware high resolution image acquisition via heterogeneous image sensors,” IEEE Journal of Selected Topics in Signal Processing, vol. 2, no. 4, pp. 526-537, August 2008.

H. Kim, D. Lee, and J. D. Villasenor, “Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection Using Sphere Decoding and LDPC Coding,” IEEE Journal on Selected Areas in Communications, vol. 26, no. 6, pp. 1003-1014, August 2008.

D. Choi, K. Choi, and J.D. Villasenor, “New Non-volatile Memory Structures for FPGA Architectures,” IEEE Transactions on VLSI Systems, vol. 16, no. 7, pp. 874-881, July 2008.

H. Kim and J. D. Villasenor, “Secure MIMO Communications in a System with Equal Numbers of Transmit and Receive Antennas,” IEEE Communications Letters, vol. 12, no. 5, pp. 386-388, May 2008.

D. Lee, H. Kim, C. Jones, and J. D. Villasenor, “Pilotless frame synchronization for LDPC-coded transmission systems,” IEEE Transactions on Signal Processing, vol. 56, no. 7, pp. 2865 – 2874, July 2008.

D. Lee, R.C.C. Cheung, J.D. Villasenor, and W. Luk, “Hardware implementation tradeoffs of polynomial approximations and interpolations,” IEEE Transactions on Computers, vol. 57, no. 5, pp. 686-701, May 2008.

D.B. Thomas, W. Luk, P.H.W. Leong, and J.D. Villasenor, “Gaussian Random Number Generators,” ACM Computing Surveys, volume 39, issue 4, article 11, Oct 2007.

D. Lee, H. Kim, C.R. Jones, and J.D. Villasenor, “Pilotless frame synchronization via LDPC code constraint feedback,” IEEE Communications Letters, volume 11, number 8, pages 683-685, Aug 2007.

R.C.C. Cheung, D. Lee, W. Luk, and J.D. Villasenor, “Hardware generation of arbitrary random number distributions from uniform distributions via the inversion method,” IEEE Transactions on VLSI Systems, volume 15, number 8, pages 952-962, Aug 2007.

H. Kim, J. Wen, and J.D. Villasenor, “Secure Arithmetic Coding,” IEEE Transactions on Signal Processing, vol. 55, no.5, pp. 2263 – 2272, May 2007.

D. Lee, R.C.C. Cheung, and J.D. Villasenor, “A flexible architecture for precise gamma correction,” IEEE Transactions on VLSI Systems, volume 15, number 4, pp. 474-479, Apr 2007.

D. Lee and J.D. Villasenor, “A bit-width optimization methodology for polynomial-based function evaluation,” IEEE Transactions on Computers, vol. 56, no. 4, pp. 567-571, Apr 2007.

C. Jones, T. Tian, J. Villasenor, and R. Wesel, “The Universal Operation of LDPC Codes over Scalar Fading Channels,” IEEE Transactions on Communications, Vol. 55, No. 1, pp.122-132, Jan 2007.

M.D. Smith and J. Villasenor, “JPEG-2000 Rate Control for Digital Cinema,” SMPTE Motion Imaging Journal, Vol. 115, No. 10, pp.394-399, Oct 2006.

D. Lee, J.D. Villasenor, W. Luk and P.H.W. Leong, “A hardware Gaussian noise generator using the Box-Muller method and its error analysis,” IEEE Transactions on Computers, vol. 55, no. 6, pp. 659-671, Jun 2006.

D. Lee, E.L. Valles, J.D. Villasenor and C.R. Jones, “Joint LDPC decoding and timing recovery using code constraint feedback,” IEEE Communications Letters, volume 10, number 3, pages 189-191, Mar 2006.

J. Wen, H. Kim and J.D. Villasenor “Binary Arithmetic Coding with Key-Based Interval Splitting,” IEEE Signal Processing Letters, vol. 13, no. 2, pp.69-72, February 2006.

D. Lee, W. Luk, J.D. Villasenor, G. Zhang and P.H.W. Leong, “A hardware Gaussian noise generator using the Wallace method,” IEEE Transactions on VLSI Systems, volume 13, number 8, pages 911-920, Aug 2005.

P.H.W. Leong, G. Zhang, D. Lee, W. Luk and J.D. Villasenor, “A Comment on the Implementation of the Ziggurat Method,” Journal of Statistical Software, volume 12, number 7, Feb 2005.